Bipolar power supply circuit designed with hot swap controller

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The so-called bipolar power supply refers to a power source that can operate from the first quadrant to the fourth quadrant. In contrast, power supplies that operate only in the first quadrant and the third quadrant can be operated. It is called a unipolar power supply. A typical DC power supply is a unipolar power supply. Some applications require the use of a hot-swap controller, a circuit breaker, or both to accommodate the mains of a bipolar DC input power supply. In some cases where a hot-swap controller is used, this requirement is only for the consideration of the starting current. To eliminate the "stress" of the connector and the interference of the mains, it is necessary to control the starting current. Other applications, such as when a power supply fails for some reason, can cause problems. The bias supply for a gallium arsenide FET amplifier is an example. If the negative gate bias is removed, the positive drain supply must also be removed. Otherwise, the amplifier will self-destruct due to excessive drain current. However, as long as a single-channel hot-swap controller is used, these two requirements can be met.

The circuit shown above uses the TPS23311D (ie IC) in a floating manner. This circuit makes the ground of lC related to the negative input voltage. If the positive rail voltage is too low or the negative rail voltage is too high, the circuit does not reach the 1.225V threshold on the VSENSE pin, so the IC turns off. There is a hysteresis voltage of approximately 30mV on the VSENSE pin to ensure no chattering when lC is turned on. When both positive and negative voltages exceed their respective thresholds. The ICI is turned on, providing a controlled slew rate for both FETs that grows linearly over time. It should be noted that this circuit uses only N-channel FETs, because the on-resistance of the N-channel FET is smaller than that of the P-channel FET, given the size and cost. In order to make QIA conductive. The lC has an internal charge pump that produces a voltage greater than the positive rail voltage, which enhances the FET. With the establishment of the gate voltage, the Q3 transistor acts as a linear level, so Q1B can also grow linearly with time, and its turn-on speed is a function of the output current and C3 value of lC 14μA. The design uses these two FETs based on the maximum allowable resistance in the DC path and the power dissipation of the FET. In fact, any size FET can be used. It depends on the amount of current that needs to be controlled. It should be noted that the total voltage range applied to lC cannot exceed the maximum rated voltage of 15V. If the voltage of lC does not float between the two input supply voltages, the debt input voltage may be relatively large. The figure below shows an application circuit with input voltages of Sv and -12V. The main requirement of this circuit is that the level shifting transistor Q3 is able to withstand higher voltages. In addition, this circuit can withstand a positive input voltage of the maximum rated voltage (15V).